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For holdover. Found Datasheets File :: 681    Search Time::1.546ms    
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    849N202CKI-DDDLF 849N202CKI-DDDLFT

Integrated Device Technology
Part No. 849N202CKI-DDDLF 849N202CKI-DDDLFT
OCR Text ... cca v ee lf1 lf0 clk_active nc holdover clk0bad ics849n202i 40 lead vfqfn 6mm x 6mm x 0.925mm k package top view pin assignment ics849n202cki revision a september 26, 2011 2 ?2011 integrated device technology, inc. ics849n202i dat...
Description FemtoClock? NG Universal Frequency Translator

File Size 1,042.83K  /  39 Page

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    Integrated Device Technology, Inc.
Part No. IDT82V3012PV
OCR Text ... f0_sel0 f0_sel1 freerun normal holdover tdo tdi mon_out0 fref1 fref0 in_sel virtual reference flock invalid input signal detection f19o c6o jtag lock mode_sel0 mode_sel1 tie_en tms trst tck v dd v ss v dd v dd v ss rst f32o feedback signal...
Description T1/E1/OC3 WAN PLL WITH DUAL REFERENCE INPUTS SPECIALTY TELECOM CIRCUIT, PDSO56

File Size 370.84K  /  30 Page

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    Maxim Integrated Products, Inc.
Part No. MAX3953UGK-D
OCR Text ...g data becomes invalid, a clock holdover function is provided to maintain a valid reference clock to the upstream device. for proper operation, a reference clock of baud rate/64 or baud rate/16 is required. the max3953 operates from a singl...
Description 10Gbps 1:16 Deserializer with Clock Recovery SPECIALTY TELECOM CIRCUIT, QCC68

File Size 242.57K  /  11 Page

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    Integrated Device Technology, Inc.
Part No. IDT82V3010PVG
OCR Text ...e of 1 s ? jtag boundary scan ? holdover status indication ? freerun status indication ? normal status indication ? lock status indication ? input reference quality indication ? 3.3 v operation with 5 v tolerant i/o ? package: 56-pin ssop (...
Description T1/E1/OC3 TELECOM CLOCK GENERATOR WITH DUAL REFERENCE INPUTS SPECIALTY TELECOM CIRCUIT, PDSO56

File Size 350.36K  /  31 Page

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    Analog Devices, Inc.
Part No. AD9547BCPZ-REEL7
OCR Text ...supports stratum 2 stability in holdover mode supports reference switchover with phase build-out supports hitless reference switchover automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair c...
Description Dual/Quad Input Network Clock Generator/Synchronizer; Package: 64-LFCSP (Leadform Chip Scale); Temperature Range: -40&#176;C to 125&#176;C 450 MHz, OTHER CLOCK GENERATOR, QCC64

File Size 966.79K  /  104 Page

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    AD9547/PCBZ

Analog Devices
Part No. AD9547/PCBZ
OCR Text ...supports stratum 2 stability in holdover mode supports reference switchover with phase build-out supports hitless reference switchover automatic/manual holdover and reference switchover 2 pairs of reference input pins, with each pair c...
Description Dual/Quad Input Network Clock Generator/Synchronizer

File Size 1,067.40K  /  104 Page

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    IDT82V3399BNLGBLANK

Integrated Device Technology
Part No. IDT82V3399BNLGBLANK
OCR Text ...upports 1.1x10 -5 ppm absolute holdover accuracy and 4.4x10 -8 ppm instantaneous holdover accuracy ? supports hitless reference switch ing to minimize phase transients on t0 dpll output to be no more than 0.61 ns ? supports programmable in...
Description SYNCHRONOUS ETHERNET WAN PLL and Clock Generation for IEEE-1588

File Size 48.07K  /  5 Page

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    AD9548/PCBZ

Analog Devices
Part No. AD9548/PCBZ
OCR Text ...supports stratum 2 stability in holdover mode supports reference switchover with phase build-out supports hitless reference switchover auto/manual holdover and reference switchover 4 pairs of reference input pins with each pair configu...
Description Quad/Octal Input Network Clock Generator/Synchronizer

File Size 1,038.27K  /  112 Page

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    ACS8510

Semtech Corporation
Part No. ACS8510
OCR Text ...e supports Free-Run, Locked and Holdover modes. It also supports all three types of reference clock source: recovered line clock, PDH network, and node synchronization. The ACS8510 generates independent SEC and BITS clocks, an 8 kHz Frame S...
Description Synchronous Equipment Timing Source for SONET or SDH Network Elements

File Size 743.97K  /  69 Page

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