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				Micron Technology
Part No.	MT41K256M16 MT41K1G4 MT41K256M16HA-125ITE MT41K512M8
OCR Text	...e enables (registered high) and disables (registered low) internal circuitry and clocks on the dram. the specific circuitry that is enabled/ disabled is dependent upon the ddr3 sdram configuration and operating mode. taking cke low provides...
Description	4Gb: x4, x8, x16 1.35V DDR3L SDRAM
File Size	576.74K / 27 Page	View it Online	Download Datasheet

				CYPRESS[Cypress Semiconductor]
Part No.	CY23FP12 CY23FP12OXC CY23FP12OXCT CY23FP12OXI CY23FP12OXIT CY3692 CY23FP12OC CY23FP12OCT CY23FP12OI CY23FP12OIT CY3672
OCR Text	...ange of 16 mA to 20 mA. Enables/disables CLKB[5:0] outputs. Each of the six outputs can be disabled Enable individually if not used, to minimize electromagnetic interference (EMI) and switching noise. Enables/disables CLKA[5:0] outputs. Eac...
Description	200-MHz Field Programmable Zero Delay Buffer
File Size	199.21K / 10 Page	View it Online	Download Datasheet

				Cermetek microelectronics Electronic Theatre Controls, Inc. ETC[ETC] List of Unclassifed Manufacturers
Part No.	CH1786 CH1786NE CH1786LCNE CH1786NH
OCR Text	...ignal on the TXD pin. ATS24=255 disables the Sleep Mode and is the default if no value is set in register S24. A SLEEP output signal is available to control power to external devices. In Figure 6, a FET controlled by the SLEEP signal turns ...
Description	Ultra small 2400bps modem CH1786 Family of Ultra Small 2400bps Modems CH1786 Family of Ultra Small 2400bps Modems
File Size	540.83K / 18 Page	View it Online	Download Datasheet

				MOTOROLA INC
Part No.	MCM64Z916ZP100R MCM64Z834ZP100R
OCR Text	...bo . 87 cke input clock enable: disables the ck input when cke is high. (a) 51, 52, 53, 56, 57, 58, 59, 62, 63 (b) 68, 69, 72, 73, 74, 75, 78, 79, 80 (c) 1, 2, 3, 6, 7, 8, 9, 12, 13 (d) 18, 19, 22, 23, 24, 25, 28, 29, 30 dqx i/o synchronou...
Description	512K X 18 ZBT SRAM, 5 ns, PBGA119 256K X 36 ZBT SRAM, 5 ns, PBGA119
File Size	360.86K / 32 Page	View it Online	Download Datasheet

				OKI electronic componets
Part No.	FEDS82V48540-01
OCR Text	...ll inputs at the "h" edge. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, dqm0, dqm1, dqm2 and dqm3. cke masks system clock to deactivate the subsequent clk operation. if cke is deac...
Description	393,216-Word × 32-Bit × 4-Bank FIFO-SGRAM
File Size	1,411.15K / 44 Page	View it Online	Download Datasheet

				Linear Technology, Corp. Linear Technology Corporation
Part No.	LTC4300-2CMS8 LTC4300-2IMS8 LTC4300-1CMS8 LTC4300-1IMS8 LTC4300-1CMS8TRPBF
OCR Text	...put pin, ACC, which enables and disables the rise-time accelerator currents. The LTC4300 is available in a small 8-pin MSOP package. APPLICATIO S s s s s Hot Board Insertion Servers Capacitance Buffer/Bus Extender Desktop Computer ...
Description	Hot Swappable 2-Wire Bus Buffers; Package: MSOP; No of Pins: 8; Temperature Range: 0°C to 70°C Hot Swappable 2-Wire Bus Buffers 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO8
File Size	285.61K / 16 Page	View it Online	Download Datasheet

				Linear Technology
Part No.	LTC4300A-1IMS8 LTC4300A-1 LTC4300A-1CMS8 LTC4300A-2 LTC4300A-2CMS8 LTC4300A-2IMS8 LTABF LTABG LTACF LTACG
OCR Text	...put pin, ACC, which enables and disables the rise-time accelerator currents. The LTC4300A is available in a small 8-pin MSOP package. APPLICATIO S s s s s Hot Board Insertion Servers Capacitance Buffer/Bus Extender Desktop Computer ...
Description	Hot Swappable 2-Wire Bus Buffers
File Size	277.06K / 16 Page	View it Online	Download Datasheet

				Motorola, Inc.
Part No.	MRFIC1854A
OCR Text	...es entire chip and Low (<0.4 V) disables chip. Mixer LO input pin. Bias select pin. Logic Low (<0.4 V) selects higher current bias for increased linearity and output power. High (>2.4 V) selects lower bias for reduced current consumption. I...
Description	1.9GHz CDMA Upmixer/Exciter Amplifier(1.9GHz CDMA上混频器/放大 CDMA Upmixer / Exciter
File Size	120.25K / 10 Page	View it Online	Download Datasheet

				XILINX
Part No.	XC17256DDD8M
OCR Text	...figuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input o...
Description	QPRO Family of XC1700D QML Configuration PROMs
File Size	82.06K / 11 Page	View it Online	Download Datasheet

For disables Found Datasheets File :: 14585 Search Time::1.594ms
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