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IDT
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| Part No. |
IDT5T2010 5T2010_DATASHEET
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| OCR Text |
...PECL input interface Selectable differential or single-ended inputs and ten singleended outputs PLL bypass for DC testing External differential feedback, internal loop filter Low Jitter: <75ps cycle-to-cycle Power-down mode Lock indicator A... |
| Description |
2.5V ZERO DELAY PLL CLOCK DRIVER TERACLOCK?
From old datasheet system
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| File Size |
154.86K /
23 Page |
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it Online |
Download Datasheet
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AGERE[Agere Systems]
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| Part No. |
LCK4801
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| OCR Text |
Differential Clock
General
The LCK4801 is a low-voltage, 3.3 V HSTL differential clock synthesizer. The LCK4801 supports two differential HSTL output pairs with frequencies from 336 MHz to 1 GHz. The clock is designed to support single an... |
| Description |
Low-Voltage HSTL Differential Clock
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| File Size |
71.45K /
10 Page |
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it Online |
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Motorola
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| Part No. |
MCM63L836A
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| OCR Text |
...ate copper CMOS technology. The differential clock (CK) inputs control the timing of read/write operations of the RAM. At the rising edge of...to accept write data on the rising edge of CK, a cycle after address and control signals. Read data ... |
| Description |
8M Late Write HSTL
From old datasheet system
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| File Size |
411.85K /
20 Page |
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it Online |
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Price and Availability
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