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ddr qdr Datasheet PDF File

For ddr qdr Found Datasheets File :: 430 Search Time::1.203ms
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				Cypress Semiconductor
Part No.	CY7C1305BV18-100BZC CY7C1305BV18-133BZC CY7C1305BV18-167BZC CY7C1307BV18-100BZC CY7C1307BV18-133BZC CY7C1307BV18-167BZC CY7C1305BV18-100BZXC CY7C1307BV18-100BZXC
OCR Text	...s frequency * Double Data Rate (ddr) interfaces on both Read & Write Ports (data transferred at 333 MHz) @167 MHz * Two input clocks (K and ...qdr architecture consists of two separate ports to access the memory array. The Read port has dedica...
Description	18-Mbit Burst of 4 Pipelined SRAM with QD(TM)Architecture 18-Mbit Burst of 4 Pipelined SRAM with qdr⑩ Architecture
File Size	241.13K / 20 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1248V18 CY7C1248V18-300BZC CY7C1248V18-300BZI CY7C1248V18-300BZXC CY7C1248V18-300BZXI CY7C1248V18-333BZC CY7C1248V18-333BZI CY7C1248V18-333BZXC CY7C1248V18-333BZXI CY7C1248V18-375BZC CY7C1248V18-375BZI CY7C1248V18-375BZXC CY7C1248V18-375BZXI CY7C1250V18-300BZC CY7C1250V18-300BZI CY7C1250V18-300BZXC CY7C1250V18-300BZXI CY7C1250V18-333BZC CY7C1250V18-333BZI CY7C1250V18-333BZXC CY7C1250V18-333BZXI CY7C1250V18-375BZC CY7C1250V18-375BZI CY7C1250V18-375BZXC CY7C1246V18-333BZC CY7C1257V18-333BZC
OCR Text	ddr-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 375...qdr consortium specification for VDDQ is 1.5V + 0.1V. The Cypress qdr devices exceed the qdr consort...
Description	36-Mbit ddr-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	1,088.29K / 27 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1514AV18 CY7C1514AV18-167BZC CY7C1514AV18-167BZI CY7C1514AV18-167BZXC CY7C1514AV18-167BZXI CY7C1514AV18-200BZC CY7C1514AV18-200BZI CY7C1514AV18-200BZXC CY7C1514AV18-200BZXI CY7C1514AV18-250BZC CY7C1514AV18-250BZI CY7C1514AV18-250BZXC CY7C1512AV18 CY7C1512AV18-167BZC CY7C1512AV18-167BZI CY7C1512AV18-167BZXC CY7C1512AV18-167BZXI CY7C1512AV18-200BZC CY7C1512AV18-200BZI CY7C1512AV18-200BZXC CY7C1512AV18-200BZXI CY7C1512AV18-250BZC CY7C1512AV18-250BZI CY7C1512AV18-250BZXC CY7C1512AV18-250BZXI
OCR Text	...ll accesses * Double Data Rate (ddr) interfaces on both Read and Write ports (data transferred at 500 MHz) @ 250 MHz * Two input clocks (K a...qdr-II operates with 1.5 cycle read latency when DLL is enabled * Operates like a qdr I device with ...
Description	72-Mbit qdr-II⑩ SRAM 2-Word Burst Architecture
File Size	1,102.50K / 26 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1515V18-167BZC CY7C1515V18-167BZI CY7C1515V18-167BZXC CY7C1515V18-167BZXI CY7C1515V18-200BZC CY7C1515V18-200BZI CY7C1515V18-200BZXC CY7C1515V18-200BZXI CY7C1515V18-250BZI CY7C1515V18-250BZXC CY7C1515V18-250BZXI CY7C1515V18-278BZC CY7C1515V18-278BZI CY7C1515V18-278BZXC CY7C1515V18-278BZXI CY7C1515V18-300BZC CY7C1515V18-300BZI CY7C1515V18-300BZXC CY7C1515V18-300BZXI
OCR Text	...s frequency * Double Data Rate (ddr) interfaces on both Read and Write Ports (data transferred at 600 MHz) at 300 MHz * Two input clocks (K ...qdr-II architecture. qdr-II architecture consists of two separate ports to access the memory array. ...
Description	72-Mbit qdr⑩- II SRAM 4-Word Burst Architecture
File Size	464.62K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1561V18 CY7C1561V18-300BZC CY7C1561V18-300BZI CY7C1561V18-300BZXC CY7C1561V18-300BZXI
OCR Text	...bus frequency Double Data Rate (ddr) interfaces on both Read and Write Ports (data transferred at 800 MHz) at 400 MHz Read latency of 2.5 cl...qdr-II+ architecture. Similar to qdr-II architecture, qdr-II+ SRAMs consists of two separate ports t...
Description	72-Mbit qdr⑩-II SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)
File Size	962.73K / 28 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1150V18-333BZC CY7C1150V18-333BZI CY7C1150V18-333BZXC CY7C1150V18-333BZXI CY7C1150V18-375BZC CY7C1150V18-375BZI CY7C1150V18-375BZXC CY7C1150V18-375BZXI CY7C1146V18-333BZC CY7C1148V18-333BZC CY7C1157V18-333BZC
OCR Text	ddr-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description The CY7C1146V18, CY7C1157V18, CY...qdr consortium specification for VDDQ is 1.5V + 0.1V. The Cypress qdr devices exceed the qdr consort...
Description	18-Mbit ddr-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	968.15K / 27 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1550V18-300BZC CY7C1550V18-300BZI CY7C1550V18-300BZXC CY7C1550V18-300BZXI CY7C1550V18-333BZC CY7C1550V18-333BZI CY7C1550V18-333BZXC CY7C1550V18-333BZXI CY7C1550V18-375BZC CY7C1550V18-375BZI CY7C1550V18-375BZXC CY7C1557V18 CY7C1557V18-300BZC
OCR Text	ddr-II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Functional Description The CY7C1546V18, CY7C1557V18, CY...qdr consortium specification for VDDQ is 1.5V + 0.1V. The Cypress qdr devices exceed the qdr consort...
Description	72-Mbit ddr-II SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency)
File Size	954.75K / 27 Page	View it Online	Download Datasheet

				Altera Corporation
Part No.	EP2S90 EP2S130 EP2S15
OCR Text	...ed, including double data rate (ddr) SDRAM and ddr2 SDRAM, RLDRAM II, quad data rate (qdr) II SRAM, and single data rate (SDR) SDRAM. Stratix II devices support various I/O standards along with support for 1-gigabit per second (Gbps) source...
Description	Stratix II Device Family
File Size	1,179.17K / 238 Page	View it Online	Download Datasheet

				Altera Corporation
Part No.	EP2SGX60C EP2SGX60D EP2SGX60E EP2SGX30C EP2SGX30D EP2SGX90E EP2SGX90F
OCR Text	... qdrII) SRAM, double data rate (ddr and ddr2) SDRAM, and single data rate (SDR) SDRAM Altera Corporation October 2007 1-1 Features Support for multiple intellectual property megafunctions from Altera(R) MegaCore(R) func...
Description	Stratix II GX Device
File Size	1,917.50K / 314 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C1307BV25-167BZC
OCR Text	...s frequency * Double Data Rate (ddr) interfaces on both Read and Write Ports (data transferred at 333 MHz) @167 MHz * Two input clocks (K an...qdr architecture. qdr architecture consists of two separate ports to access the memory array. The Re...
Description	18-Mbit Burst of 4 Pipelined SRAM with qdr⑩ Architecture
File Size	917.08K / 21 Page	View it Online	Download Datasheet

For ddr qdr Found Datasheets File :: 430 Search Time::1.203ms
Page :: | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 | 9 | 10 | <11> | 12 | 13 | 14 | 15 |