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    ST Microelectronics
Part No. ST20196
OCR Text ...ayer has been implemented. the cached arm? micro-controller allows further improvement of the performances and allows fast and easy integration with the major third party network processors. data is exchanged over the utopia level1 or 2 in...
Description ADSL2 UTOPIA DMT TRANSCEIVER FOR CPE APPLICATIONS

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    FREESCALE[Freescale Semiconductor, Inc]
Part No. MCF5253VM140 MCF5253
OCR Text ...system performance by providing cached instructions to the execution unit in a single clock cycle. The two-wire I2C bus interfaces, compliant with the Philips I2C bus standard, are bidirectional serial buses that exchange data between devic...
Description ColdFire㈢ Microprocessor Data Sheet

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    MCF5206

Motorola, Inc
Part No. MCF5206
OCR Text ...system performance by providing cached instructions to the execution unit in a single clock. The MCF5206 processor uses a 512-byte, direct-mapped instruction cache to achieve 17 MIPS at 33 Mhz.The cache is accessed by physical addresses, wh...
Description MCF5206 Integrated Microprocessor
MCF5206 Integrated Microprocessor

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    Bourns, Inc.
Part No. PPC403GB-KA28C-1
OCR Text ...rations. the cache can send two cached instructions per cycle to the execution unit, allowing instructions to be folded out of the queue without interrupting normal instruction flow. when a branch instruc- tion is folded and executed in ...
Description 32-Bit Microprocessor 32位微处理

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    飞思卡尔半导体(中国)有限公司
椋???″????浣?涓??)??????
Part No. MCF5251 MCF5251CEVM140
OCR Text ...ystem performance by providing cached instructions to the execution unit in a single clock cycle. i 2 c inter ic communication module connectivity peripheral the two-wire i 2 c bus interfaces, compliant with the philips i 2 c bus st...
Description ColdFire Processor

File Size 284.26K  /  32 Page

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    飞思卡尔半导体(中国)有限公司
Part No. MCF5253
OCR Text ...ystem performance by providing cached instructions to the execution unit in a single clock cycle. i 2 c inter ic communication module connectivity peripheral the two-wire i 2 c bus interfaces, compliant with the philips i 2 c bus st...
Description ColdFireMicroprocessor Data Sheet

File Size 229.05K  /  32 Page

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    Motorola
Part No. MPC566
OCR Text ...n optimized for automotive (non-cached) applications ? new compression scheme increases compression performance to 40% ? 50% compres- sion ? 4-kbyte static decram can be used as memory if compression is not used. ? general-purpose i/o suppo...
Description (MPC565 / MPC566) RISC MCU

File Size 135.84K  /  12 Page

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    WED3C750A8M-200BX

White Electronic Designs Corporation
Part No. WED3C750A8M-200BX
OCR Text ... from the l1 data cache can be cached in the l2 cache, which treats all transactions from the l1 instruction cache as cache-inhibited (bypass l2 cache, no l2 checking done). l2 data-only depends on application. 10 l2i l2 global invalidate...
Description RISC Microprocessor Module(精简指令集计算机微处理器模块)

File Size 334.21K  /  10 Page

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