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ELPIDA[Elpida Memory]
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| Part No. |
EDD1216AATA-5C-E EDD1216AATA-5 EDD1216AATA-5B-E
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| OCR Text |
...,VDDQ = 2.6V 0.1V * Data rate: 400mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver * Data i... |
| Description |
128M bits DDR SDRAM (8M words x 16 bits, DDR400)
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| File Size |
535.80K /
48 Page |
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it Online |
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ELPIDA[Elpida Memory]
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| Part No. |
EDD2508AKTA-5C-E EDD2508AKTA-5B-E EDD2508AKTA-5-E
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| OCR Text |
... VDDQ = 2.6V 0.1V * Data rate: 400mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outpu... |
| Description |
256M bits DDR SDRAM (32M words x 8 bits, DDR400)
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| File Size |
531.21K /
48 Page |
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it Online |
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ELPIDA[Elpida Memory]
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| Part No. |
EDD2508AKTA-5C EDD2508AKTA-5 EDD2508AKTA-5B
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| OCR Text |
...: VDD = 2.6V 0.1V * Data rate: 400mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional, data strobe (DQS) is transmitted /received with data, to be used in capturing data at the receiver * Data i... |
| Description |
256M bits DDR SDRAM (32M words x 8 bits, DDR400)
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| File Size |
528.16K /
48 Page |
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it Online |
Download Datasheet |
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ELPIDA[Elpida Memory]
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| Part No. |
EDD5116ADTA-5C EDD5108ADTA-5C
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| OCR Text |
...,VDDQ = 2.6V 0.1V * Data rate: 400mbps (max.) * Double Data Rate architecture; two data transfers per clock cycle * Bi-directional data strobe (DQS) is transmitted /received with data for capturing data at the receiver * Data inputs, outpu... |
| Description |
512M bits DDR SDRAM
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| File Size |
533.22K /
48 Page |
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it Online |
Download Datasheet |
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Samsung Semiconductor Co., Ltd.
SAMSUNG SEMICONDUCTOR CO. LTD.
SAMSUNG[Samsung semiconductor]
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| Part No. |
K4H560838E-GCCC K4H560438E-GCC4 K4H560438E-GCCC K4H560838E-GCC4
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| OCR Text |
...
Key Features
* 200MHz Clock, 400mbps data rate. * VDD= +2.6V + 0.10V, VDDQ= +2.6V + 0.10V * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe [DQ] (x4,x8) * Four banks operation * Differential ... |
| Description |
DIODE ZENER SINGLE 300mW 27Vz 5mA-Izt 0.02503 0.05uA-Ir 21 SOT-23 3K/REEL 256Mb的电子芯片的DDR 400内存规格60Ball FBGA封装（x4/x8
DIODE ZENER SINGLE 300mW 29.8Vz 5mA-Izt 0.02503 0.05uA-Ir 23 SOT-23 3K/REEL
256Mb E-die DDR 400 SDRAM Specification 60Ball FBGA (x4/x8)
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| File Size |
195.42K /
18 Page |
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it Online |
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IDT
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| Part No. |
IDT72T55268 IDT72T55258
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| OCR Text |
...ta input pin has a bandwidth of 400mbps. So for a 40-bit wide bus a total bandwidth of 16Gbps can be achieved. In Mux mode operation a 4:1 architecture is setup, (four input ports to one output port). Here there are four internal Sequential... |
| Description |
2.5V QUADMUX DDR FLOW-CONTROL DEVICE
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| File Size |
518.72K /
63 Page |
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it Online |
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PERICOM[Pericom Semiconductor Corporation]
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| Part No. |
PI90LV032A PI90LV017A PI90LV018A PI90LV027A PI90LV028A PI90LV031A
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| OCR Text |
...
Features
* Signaling Rates >400mbps (200 MHz) * Single 3.3V Power Supply Design * 350mV Differential Swing * Maximum Differential Skew of 0.4ns * Maximum Propagation Delay of 2.0ns * Maximum Power Dissipation: 25mW @ 200 MHz/driver * Lo... |
| Description |
3V LVDS High-Speed Differential Line Drivers
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| File Size |
322.46K /
10 Page |
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it Online |
Download Datasheet |
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Price and Availability
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